IDT82V3202NLG【PDF 44/117 页】IC PLL WAN EBU SGL 68-VFQFPN

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IDT82V3202

EBU WAN PLL

Functional Description

September 11, 2009

phase locked to any input clock. The frequency offset acquiring method

is selected by the MAN_HOLDOVER bit, the AUTO_AVG bit and the

FAST_AVG bit, as shown in Table 17:

3.10.1.5.1 Automatic Instantaneous

By this method, the T0 DPLL freezes at the operating frequency

when it enters Holdover mode. The accuracy is 4.4X10-8 ppm.

3.10.1.5.2 Automatic Slow Averaged

By this method, an internal IIR (Infinite Impulse Response) filter is

employed to get the frequency offset. The IIR filter gives a 3 dB attenua-

tion point corresponding to a period of 110 minutes. The accuracy is

1.1X10-5 ppm.

3.10.1.5.3 Automatic Fast Averaged

By this method, an internal IIR (Infinite Impulse Response) filter is

employed to get the frequency offset. The IIR filter gives a 3 dB attenua-

tion point corresponding to a period of 8 minutes. The accuracy is

1.1X10-5 ppm.

3.10.1.5.4 Manual

By this method, the frequency offset is set by the

T0_HOLDOVER_FREQ[23:0] bits. The accuracy is 1.1X10-5 ppm.

The frequency offset of the T0 DPLL output is indicated by the

CURRENT_DPLL_FREQ[23:0] bits.

The device provides a reference for the value to be written to the

T0_HOLDOVER_FREQ[23:0] bits. The value to be written can refer to

the value read from the CURRENT_DPLL_FREQ[23:0] bits or the

T0_HOLDOVER_FREQ[23:0] bits (refer to Chapter 3.10.1.5.5 Holdover

Frequency Offset Read); or then be processed by external software fil-

tering.

3.10.1.5.5 Holdover Frequency Offset Read

The offset value, which is acquired by Automatic Slow Averaged,

Automatic Fast Averaged and is set by related register bits, can be read

from the T0_HOLDOVER_FREQ[23:0] bits by setting the READ_AVG

bit and the FAST_AVG bit, as shown in Table 18.

The frequency offset in ppm is calculated as follows:

Holdover Frequency Offset (ppm) = T0_HOLDOVER_FREQ[23:0] X

0.000011

3.10.1.6

Pre-Locked2 Mode

In Pre-Locked2 mode, the T0 DPLL output attempts to track the

selected input clock.

The Pre-Locked2 mode is a secondary, temporary mode.

Table 17: Frequency Offset Control in Holdover Mode

MAN_HOLDOVER

AUTO_AVG

FAST_AVG

Frequency Offset Acquiring Method

don’t-care

Automatic Instantaneous

Automatic Slow Averaged

Automatic Fast Averaged

don’t-care

Manual

Table 18: Holdover Frequency Offset Read

READ_AVG FAST_AVG

Offset Value Read from

T0_HOLDOVER_FREQ[23:0]

don’t-care The value is equal to the one written to.

The value is acquired by Automatic Slow Averaged

method, not equal to the one written to.

The value is acquired by Automatic Fast Averaged

method, not equal to the one written to.

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